R&D Engineering, Staff Engineer

Systems Design Group at Synopsys is looking for an R&D engineer to work on the compiler for its FPGA-based Prototyping Systems.

Responsibilities:

• Responsible for research and development of Logic and Physical synthesis, netlist partitioning, placement and routing optimizations.
• Responsible for developing, testing and tuning  EDA (FPGA) algorithms through AI/ML for targeting high quality of results (QoR) such as area, performance, congestion, compile time and power etc.
• Exercises judgment to determine appropriate action. Implementations and solutions are reviewed for accuracy and overall adequacy.
• Builds productive internal/external working relationships.
• Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.

 
Requirements:

• PhD or master’s degree in electrical and/or Computer Engineering with 2+ years or bachelor’s degree with 5+ years of relevant experience.
• Solid in Machine Learning/Artificial Intelligence.
• Solid Understanding of IC Design Flows for FPGA/ASIC
• Skillful in using script languages such as TCL, Python, Perl, Unix shell scripts.
• EDA knowledge and experience in areas such logical and physical synthesis, RTL, simulation, emulation, formal verification etc is a plus.
• Background in C++ and problem-solving skills.
• Background in netlist optimizations for area, performance, congestion, power etc.
• Original research publications in the area of computer engineering / electronic design and verification field is a big plus.
• Experience with developing software into a large code bases desired
• Familiarity with industrial standard SW development and quality practices.
• Results-driven, agility, integrity and teamwork. Desire to learn and explore unfamiliar concepts, tools and techniques.
• Excellent communication skills, verbal and written. Ability to coordinate discussions with other R&D teams.