ASIC Verification Solution Lead:

Duties

• Understand Complete ASIC Design Verification Flow and Customize according to end Application.
• Build a Complete Verification flow using an existing design from RTL to GDS.
• Modify Methodology/Constraints to accommodate our Recommended Verification Flow
• Define data trends and build checkers to validate the flow.
• Automate Complete Solution, with self-monitoring trend analytics and Regression trends.

Required Qualifications

• BS or MS degree in Computer Science, Electrical or Computer Engineering, or Related Field with 7+ years of experience
• Knowledge of Digital design verification(Dynamic/Static),  Verilog/VHDL and associated verification tools.
• Experience in Complete Verification Methodology and understand what’s needed from verification perspective to Signoff a design.
• Proven HDL experience in SystemVerilog/HDL/SVA and UVM methodology
• Software experience with Python/C++/TCL scripting knowledge