Analog Design, Principal Engineer

We're looking for a Principal Analog Design Engineer to join our team.
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In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET and gate all around process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Job Responsibilities

• Review SerDes standards to develop novel transceiver architectures and sub-block specifications.
• Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets.
• Work across project and department teams to streamline design and verification strategies ensure overall design quality, efficiency and performance.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Present & review simulation data from internal project teams. Present results externally at industry panels or at customer reviews.
• Document design features and test plans.
• Consult on the overall electrical characterization of the SerDes IP product. Analyze customer silicon data for design enhancements. Propose solutions for post-silicon design updates.

Job Requirements
•MTech/MS with 12+ years, Btech/BS with 14+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study
•Experience with FinFET technologies
•In depth familiarity with transistor level circuit design - sound CMOS design fundamentals, experience with CMOS tape-outs
•Good understanding of Multi Gbps range High speed designs including PAM4 SerDes Architectures
•Extensive design experience with at least one, and familiarity with several other SerDes sub-circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, DLL, BGR, Regulators, Injection locked oscillators, ADC, DAC etc)
•Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
•Aware of ESD issues (ie. circuit techniques, layout)
•Familiarity with custom digital design (ie. high speed logic paths)
•Knowledge of design for reliability (ie. EM, IR, aging, self heating etc…)
•Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…)
•Experience with tools for schematic entry, physical layout, and design verification
•Knowledge of SPICE simulators and simulation methods
•Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc…)
•Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc…)
•Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise)
•Good communication and documentation skills