Join a growing team at Synopsys Romania with challenging projects and responsibilities.
Seeking a highly motivated and innovative engineer with background in high-speed protocols and the wish to grow on protocol knowledge by verification related work, working as part of an experienced digital design and verification team.
The position offers an excellent opportunity to work with experts on several fields. Joining this team, you will be involved in specification, verification and implementation phases of state-of-the-art products. It will involve identifying verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …), generating verification test plan, verifying environment documentation and testing environment usage documentation. It will include also defining, developing, and verifying complex UVM verification environments.
We are looking for candidates with proven desire to learn and explore new state-of-the-art technologies, with the knowledge of Verilog, VHDL and/or SystemVerilog and scripting languages such as BASH/TCSH/PERL/PYTHON/TCL and verification methodology (UVM).
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