Seeking a highly motivated and innovative digital design engineer with knowledge of Digital design, and Synthesis constraints. The candidate would be working as part of a highly experienced digital design team, targeting the current and next generation High Speed SERDES, such as USB, PCIe, Ethernet, DP2.0, HDMI2.1
Job Requirements
- Good understanding of ASIC digital design flow with hands on experience in:
- HDL coding
- Synthesis Constraints and Basics of STA
- Lint/CDC/RDC knowledge
- Working knowledge in scripting languages like Perl/Shell/Python/Tcl
- Knowledge of High Speed Serdes Protocols/RTL is an advantage
What the candidate will do
- Implement RTL in Verilog and run Spyglass CDC/RDC/Lint/ Tmax
- Work on Synthesis constraints
- Work on digital design flows
Experience : 3+ year experience
Education : B.E/B.Tech/M.Tech in ECE/EE
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