R&D Engineering, Sr Engineer

Synopsys ZeBu Server is a very high-capacity emulator system with easy setup and debugging. ZeBu emulator supports various software and hardware debugging modes. It can handle the most challenging verification problems that  can occur in the systems during the design cycle. Synopsys HAPS® Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Synopsys delivers ProtoCompiler and HAPS solution, which dramatically accelerate software development, hardware verification and system validation from single IP blocks to processor subsystems to complete SoCs.
 
 We’re looking for a Staff R&D engineer in UPF R&D team for both Zebu and HAPS software support in Bangalore for the following role and with the given background/skill sets.
Roles and responsibility:
·A person in the position would be responsible for designing, developing, troubleshooting, debugging, and maintaining large and efficient software systems.
· Work involves netlist traversal, multithreaded processing, UPFinstrumentation, optimization and API based runtime support.
·The person is expected to
o    Write requirement and functional specifications, design and implement efficient data structures and algorithms in C/C++.
o    Incorporate advanced software engineering tools and processes related to documentation and coding practices, memory and runtime profiling, coverage, unit testing in the development process.
o    Work with PV team in test planning, execution and customer support.
o    Maintain and support existing product and features.
o    Would be able to work in large and complex design automation environment.
Expected background and skill:
 The person is expected to have:
·B.Tech/M. Tech in CS/EE from a reputed institute.
·4+ yearsof experience in designing, developing and maintaining large EDA software.
·Expertise in data structures, graph algorithms and C/C++ programming on Windows/Unix.
· Solid background in netlist data structure, netlist traversal and modification.
·Good knowledge of Verilog and VHDL HDL/RTL languages and digital design.UPF knowledge is preferred.
·Experience with tools such asCoverity, valgrindetc.
·Working knowledge of FPGA prototyping tools and flows.