BE/BTech/MTech/MS in Electronics Engineering with 5+ years of experience.
MTech/MS in Electronics Engineering with 4+ years of experience.
Associated with Verification especially using industry-standard protocols & methodology.
VIP development: At least completed 2 VIP development and maintenance cycles.
Protocol experience: Should have experience with Display Port/HDMI/MIPI/USB/PCI-E protocol preferably the latest specifications.
Languages: Hands-on experience with System Verilog & Verilog. Should have good knowledge of Object-Oriented Programming(UVM).
Languages: Python, TCL, or shell Scripting is plus.
Job responsibilities
Able to individually contribute to the development of the VIP.
Responsible & can be relied for review sign off VIP development and updates from technical perspective including methodology and protocol functional prospective.
Works on problems of diverse scope where analysis of situations or data requires evaluation of identifiable factors. Exercises judgment in selecting methods and techniques to obtain solutions. Execute projects from start to completion. Contributes to moderately complex aspects of a project.
Liaison with Architects/methodology experts to achieve resolutions on issues or driving decisions from an architecture/methodology perspective.
Our Technology, Your Innovation
Synopsys is the leading silicon to systems design solutions company. Synopsys accelerates technology innovation, from silicon to systems.
Synopsys delivers the most...
Apply Now