staff engineer

ob Description: 

FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier, ProtoCompiler, Certify and Identify. These products are widely used in the industry for implementation of FPGA designs, prototyping and debugging of ASICs using FPGAs. Logic synthesis software, which is part of Synplify Pro and Synplify Premier products, is the industry standards for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. 

Looking for a Senior R&D engineer in ProtoCompiler R&D team in Bangalore for the following role and with the given background/skill sets. 

Roles and responsibility: 

• A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for Prototyping from RTL to FPGA bit stream generation. Work involves RTL compilation & optimization, partitioning designing, timing analysis for inter and intra-FPGA paths, technology mapping, logic and timing optimization steps.  

• The person is expected to 

• Write requirement and functional specifications, design and implement efficient data structures and algorithms in C/C++. 

• Incorporate advanced software engineering tools and processes related to documentation and coding practices, memory and runtime profiling, coverage, unit testing in the development process. 

• Work with CAE team in test planning, execution and customer support. 

• Maintain and support existing product and features. 

• Would be able to work in large and complex design automation environment. 

Expected background and skill: 

The person is expected to have: 

• B.Tech/M. Tech in CS/EE from a reputed institute. 

• 8+ years of experience in designing, developing and maintaining large EDA software.  

• Solid background in digital logic design. 

• Expertise in data structures, graph algorithms and C/C++ programming on Windows/Unix. 

• Good familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis. 

• Working knowledge of FPGA prototyping, design tools and flows. 

• Experience with tools such as gprof, purify, coverity etc.